Wireless communication technologies, for example, the Wireless Local Area Network (WLAN) technology, Wireless Personal Area Network (WPAN) technology, and Wireless Wide Area Network (WWAN) technology, mostly use the Orthogonal Frequency Division Multiplexing (OFDM) technology to improve the transmission throughput, and usually adopt a tail-biting convolutional code (TBCC) as an error control code.
In a decoding circuit of the error control code, several methods have been proposed to manage paths related to transferring storage state during a decoding process, but these methods all require a large capacity memory. A TBCC decoder module usually has high power consumption in a wireless communication device, so TBCC demodulation must be well designed. The TBCC decoding methods in the conventional art mainly include following two approaches such as a trace back decoding manner and a trace forward decoding manner.
In the conventional TBCC decoding method, after a receiving end receives a signal, based on a circular property of the TBCC, data in the front part of the TBCC is appended to the back part, and then a convergence stage and an initial state are found by the trace forward manner. Next, the memory stores and decodes a survivor path in each state, and stores and decodes a path metric accumulated at each stage. Finally, a maximum likelihood path is found through comparison, and a decoded correct code is read from the memory.
In addition to finding the convergence level (or a convergence stage) or the initial state in the trace forward manner, in the conventional art, the initial state of the TBCC can also be found by the trace back convergence manner. After the convergence, the data is written in the memory. Finally, the preferred path solution is found by a comparison circuit, and then the decoding process of the convolutional code is controlled by the trace back memory.
However, in the conventional art, when the TBCC is decoded, the large capacity memory may usually required, and this results in a large hardware area and consequent high power consumption. Therefore, it is an important issue to design an error control code digital circuit having high performance and lower power consumption to implement the TBCC decoding process.